This invention relates to dynamic random access memories (DRAMs). More particularly, this invention relates to power distribution on DRAMs.
A DRAM is a form of semiconductor random access memory (RAM) commonly used as main memory in computers and other electronic systems. DRAMs store information in arrays of integrated circuits that include capacitors. Because capacitors lose their charge over time, they need to be regularly recharged. This regular recharging is performed during “refresh” cycles.
DRAMs also include other circuits and devices, known as peripherals, that support memory read and write operations as well as other DRAM functions. High speed DRAMs, known as synchronous DRAMs (SDRAMs), use clocks to synchronize control and data signal transfers and include peripherals known as delay lock loop (DLL) circuits to maintain that synchronization.
DLL circuits, however, are susceptible to power and ground bus noise typically generated by the memory arrays during row activations and data reads and writes. This susceptibility can cause the DRAM to lose synchronization. Loss of synchronization causes timing problems that can result in the wrong data being read from or written to memory, thus adversely affecting data integrity throughout a computer or other system.
One known solution is to isolate the power and ground buses connected to the DLL and other synchronization control circuits from the power and ground buses connected to the DRAM arrays. This can be done by running separate power and ground buses to peripheral circuits from one set of chip power and ground input/output (I/O) pads and running separate power and ground buses to the arrays from another set of chip power and ground I/O pads. Each chip power and ground pad is connected to an external voltage. Thus, rather than have a network of power and ground buses commonly connected to all respective power and ground pads, separate and isolated power and ground buses are connected to respective subsets of the DRAM chip's power and ground pads.
Such power distribution, however, results in less available current per separate power bus, because each bus has fewer pads connected to it from which to draw current. Each power pad can supply only a limited amount of current. This can adversely affect the DRAM arrays during refresh cycles when significantly increased amounts of current are needed to recharge the capacitors. With less current available, the capacitors may not fully charge. This can decrease the time that a capacitor retains the correct stored value, thus resulting in either a loss of stored data or more frequent refresh cycles. More frequent refresh cycles result in reduced DRAM performance, because read/write operations cannot be performed during refresh cycles.
In view of the foregoing, it would be desirable to provide synchronization control circuits with power and ground busing having inconsequential, if any, noise generated by memory arrays during row activations and read/write operations while still providing the arrays with sufficient current during refresh cycles.